The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory).
A semiconductor memory device called DRAM requires rewriting of memory cells and precharging of bit lines in every cycle time. Therefore, the cycle time required by the DRAM is about twice the access time. There is technology for reducing the cycle time to approximately the same length as that of the access time by apparently hiding precharge operation of the bit lines. One example of this technology is to cause two internal ports to interleave with each other by using the memory cells each including two transistors and a single capacitor. FIG. 19 schematically shows the structure of a DRAM using this technology. Each memory cell MC1 to MC4 of the DRAM includes two transistors Ta, Tb and a single capacitor C. This DRAM causes the following two ports A, B to interleave with each other: the port A formed by the path including transistor Ta, bit line BLa1 or BLa2, data bus DBa, and read amplifier and write driver 1103a; and the port B formed by the path including transistor Tb, bit line BLb1 or BLb2, data bus DBb, and read amplifier and write driver 1103b. Hereinafter, interleave operation will be described regarding the case where data is read from a memory cell.
A row decoder 1101 activates a word line WLa1, whereby the transistors Ta of the memory cells MC1, MC3 are turned ON. As a result, data stored in the capacitors C of the memory cells MC1, MC3 are read to the bit lines BLa1, BLa2 and then amplified by a sense amplifier (not shown). A column decoder 1102a selects the bit line BLa1 and connects the bit line BLa1 to the data bus DBa. As a result, the data read from the memory cell MC1 to the bit line BLa1 is transferred to the data bus DBa. The data read to the bit lines BLa1, BLa2 are rewritten to the memory cells MC1, MC3. The row decoder 1101 then inactivates the word line WLa1, whereby the transistors Ta of the memory cells MC1, MC3 are turned OFF. The bit lines BLb1, BLb2 are precharged during the above operation.
The data transferred to the data bus DBa is amplified by the read amplifier and write driver 1103a for output to an input/output (I/O) buffer 1104. The I/O buffer 1104 outputs the amplified data to the outside. On the other hand, the row decoder 1101 activates a word line WLb2, whereby the transistors Tb of the memory cells MC2, MC4 are turned ON. As a result, data stored in the capacitors C of the memory cells MC2, MC4 are read to the bit lines BLb1, BLb2 and amplified by a sense amplifier (not shown).
A column decoder 1102b selects the bit line BLb1 and connects the bit line BLb1 to the data bus DBb. As a result, the data read from the memory cell MC2 to the bit line BLb1 is transferred to the data bus DBb. The data read to the bit lines BLb1, BLb2 are rewritten to the memory cells MC2, MC4. The row decoder 1101 then inactivates the word line WLb2, whereby the transistors Tb of the memory cells MC2, MC4 are turned OFF. The bit lines BLa1, BLa2 are precharged during the above operation.
The data transferred to the data bus DBb is amplified by the read amplifier and write driver 1103b for output to the I/O buffer 1104. The I/O buffer 1104 outputs the amplified data to the outside.
Such interleave operation of the two internal ports apparently hides precharge operation of the bit lines, thereby reducing the cycle time to approximately the same length as that of the access time.
The DRAM of FIG. 19 has a read amplifier and write driver for each port. In other words, the DRAM of FIG. 19 has a read amplifier and write driver 1103a for the port A and a read amplifier and write driver 1103b for the port B. This increases the area of peripheral circuitry including the read amplifiers and write drivers if a specification using a large bit width is required (e.g., an embedded DRAM).
It is an object of the present invention to provide a semiconductor memory device enabling reduction in layout area.
According to one aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of first and second word lines, and a plurality of first and second bit lines. The plurality of memory cells are arranged in rows and columns. The plurality of first and second word lines are arranged in the rows. The plurality of first and second bit lines are arranged in the columns. Each of the plurality of memory cells includes a first transistor, a second transistor and a capacitor. The first transistor is connected between a corresponding first bit line and the capacitor and receives a voltage on a corresponding first word line at its gate. The second transistor is connected between a corresponding second bit line and the capacitor and receives a voltage on a corresponding second word line at its gate. The semiconductor memory device further includes a data line, a plurality of first and second column selection switches, a word line driver, a column selection circuit, an input/output (I/O) buffer, and a data transfer circuit. The plurality of first column selection switches are provided corresponding to the plurality of first bit lines, and each connects and disconnects a corresponding first bit line to and from the data line. The plurality of second column selection switches are provided corresponding to the plurality of second bit lines, and each connects and disconnects a corresponding second bit line to and from the data line. The word line driver drives first and second word lines corresponding to a memory cell to be accessed. The column selection circuit turns ON/OFF first and second column selection switches corresponding to the memory cell to be accessed. The I/O buffer receives and outputs data from and to the outside. The data transfer circuit transfers data read from a memory cell to the data line to the I/O buffer and transfers write data from the I/O buffer to the data line. The word line driver and the column selection circuit conduct interleave operation, and the data transfer circuit and the I/O buffer do not conduct interleave operation.
In the above semiconductor memory device, peripheral circuitry including the data transfer circuit is required for only one port, thereby enabling reduction in layout area.
Preferably, the data line includes a write data line and a read data line. Each of the plurality of first and second column selection switches connects and disconnects a corresponding bit line to and from the write data line in order to write data to a memory cell. Each of the plurality of first and second column selection switches connects and disconnects the corresponding bit line to and from the read data line in order to read data from a memory cell.
In the above semiconductor memory device, the read data line need only be controlled for read operation, and the write data line need only be controlled for write operation. This facilitates control of the write data line and the read data line and timing design as compared to the case where a single data line is controlled for both read and writ operations.
Preferably, the data line is a single-type data line. The above semiconductor memory device eliminates the need to consider precharge operation of the bit lines, enabling quick design.
According to another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of first and second word lines, and a plurality of first and second bit lines. The plurality of memory cells are arranged in rows and columns. The plurality of first and second word lines are arranged in the rows. The plurality of first and second bit lines are arranged in the columns. Each of the plurality of memory cells includes a first transistor, a second transistor and a capacitor. The first transistor is connected between a corresponding first bit line and the capacitor and receives a voltage on a corresponding first word line at its gate. The second transistor is connected between a corresponding second bit line and the capacitor and receives a voltage on a corresponding second word line at its gate. The semiconductor memory device further includes first and second data lines, a plurality of first and second column selection switches, a word line driver, a column selection circuit, an input/output (I/O) buffer, a data transfer circuit, and a switching means. The plurality of first column selection switches are provided corresponding to the plurality of first bit lines, and each connects and disconnects a corresponding first bit line to and from the first data line. The plurality of second column selection switches are provided corresponding to the plurality of second bit lines, and each connects and disconnects a corresponding second bit line to and from the second data line. The word line driver drives first and second word lines corresponding to a memory cell to be accessed. The column selection circuit turns ON/OFF first and second column selection switches corresponding to the memory cell to be accessed. The I/O buffer receives and outputs data from and to the outside. The switching means transfers data read from a memory cell to the first or second data line to the data transfer circuit, and transfers the data from the data transfer circuit to the first or second data line. The data transfer circuit transfers data from the switching means to the I/O buffer, and transfers data from the I/O buffer to the switching means. The word line driver, the column selection circuit and the switching means conduct interleave operation, and the data transfer circuit and the I/O buffer do not conduct interleave operation.
In the above semiconductor memory device, peripheral circuitry including the data transfer circuit is required for only one port, thereby enabling reduction in layout area.
Moreover, the first and second data lines provided on the memory cell arrays and subjected to relatively large load conduct interleave operation. This enables the semiconductor memory device to be designed with a data transfer margin.
Preferably, the semiconductor memory device further includes a read data line and a write data line. The read data line is a data line for transferring data from the switching means to the I/O buffer. The write data line is a data line for transferring data from the I/O buffer to the switching means.
In the above semiconductor memory device, the read data line need only be controlled for read operation, and the write data line need only be controlled for write operation. This facilitates control of the write data line and the read data line and timing design as compared to the case where a single data line is controlled for both read and writ operations.
According to still another aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a data line pair, a decoder, a write circuit, a plurality of first to fourth transistors and a column selection circuit. The plurality of memory cells are arranged in rows and columns. The plurality of word lines are arranged in the rows. The plurality of bit line pairs are arranged in the columns. The decoder generates an active signal when data is written to any of the plurality of memory cells. The write circuit is responsive to the active signal from the decoder, and activates one or the other data line of the data line pair according to write data. The plurality of first transistors are connected between one data line of the data line pair and one bit lines of the plurality of bit line pairs, and turned ON/OFF in response to a voltage on the one data line of the data line pair. The plurality of second transistors are connected between the other data line of the data line pair and the other bit lines of the plurality of bit line pairs, and turned ON/OFF in response to a voltage on the other data line of the data line pair. The plurality of third transistors are connected between the plurality of first transistors and one bit lines of the plurality of bit line pairs. The plurality of fourth transistors are connected between the plurality of second transistors and the other bit lines of the plurality of bit line pairs. The column selection circuit applies an active signal to a gate of one of the plurality of third transistors which corresponds to a bit line pair corresponding to a memory cell to be written and applies an active signal to a gate of one of the fourth transistors which corresponds to the bit line pair.
In the above semiconductor memory device, the plurality of first and second transistors for transferring data from the data line pair to the bit line pair are turned ON/OFF by the voltage on the data line pair. As a result, signal lines for turning ON/OFF the plurality of first and second transistors need not be provided in the column direction.
This enables reduction in layout area of wiring layers.
Moreover, power supply lines can be provided instead of the signal lines for turning ON/OFF the plurality of first and second transistors. This not only reinforces the power supply but also improves the shielding effect of the data line pair.
Preferably, the plurality of first transistors are turned ON/OFF in response to a voltage on the other data line of the data line pair instead of the voltage on the one data line of the data line pair, and the plurality of second transistors are turned ON/OFF in response to a voltage on the one data line of the data line pair instead of the voltage on the other data line of the data line pair.
The above semiconductor memory device prevents a write voltage to the bit line pair from being varied by a threshold voltage of the first or second transistor.
According to yet another aspect of the present a semiconductor memory device includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a data line pair, a decoder, a write circuit, a plurality of first to fourth transistors, and a column selection circuit. The plurality of memory cells are arranged in rows and columns. The plurality of word lines are arranged in the rows. The plurality of bit line pairs are arranged in the columns. The decoder generates an active signal when data is written to any of the plurality of memory cells. The write circuit is responsive to the active signal from the decoder, and activates one or the other data line of the data line pair according to write data. The plurality of first transistors are connected between a node receiving a power supply voltage or a ground voltage and one bit lines of the plurality of bit line pairs, and are turned ON/OFF in response to a voltage on one data line of the data line pair. The plurality of second transistors are connected between the node and the other bit lines of the plurality of bit line pairs, and are turned ON/OFF in response to a voltage on the other data line of the data line pair. The plurality of third transistors are connected between the plurality of first transistors and one bit lines of the plurality of bit line pairs. The plurality of fourth transistors are connected between the plurality of second transistors and the other bit lines of the plurality of bit line pairs. The column selection circuit applies an active signal to a gate of one of the plurality of third transistors which corresponds to a bit line pair corresponding to a memory cell to be written and applies an active signal to a gate of one of the fourth transistors which corresponds to the bit line pair.
In the above semiconductor memory device, the plurality of first and second transistors for transferring data to the bit line pair are turned ON/OFF by the voltage on the data line pair. As a result, signal lines for turning ON/OFF the plurality of first and second transistors need not be provided in the column direction. This enables reduction in layout area of wiring layers.
Moreover, a circuit for precharging the data line pair is not required, enabling reduction in layout area and power consumption.
Preferably, the first and second transistors are CMOS (Complementary Metal Oxide Semiconductor) transistors.
Preferably, the above semiconductor memory device further includes a sense amplifier for amplifying a potential difference of a bit line pair corresponding to a memory cell to be written after the bit line pair is driven according to write data.
Preferably, the semiconductor memory device further includes a precharge circuit. The precharge circuit precharges a bit line pair corresponding to a memory cell to be written for a predetermined period after the bit line pair is driven according to write data until the sense amplifier amplifies a potential difference of the bit line pair.
In the above semiconductor memory device, the bit line to which data is read from the memory cell is pulled up or pulled down to the precharge level. This ensures the potential difference between the bit lines at least in read operation, whereby a sufficient write operation margin is obtained.
According to a further aspect of the present invention, a semiconductor memory device includes a first main amplifier, a first tri-state buffer, and a first latch circuit. The first main amplifier is activated in response to an active first enable signal, and amplifies data read from a first memory cell. When the first enable signal is active, the first tri-state buffer drives an output node of the first tri-state buffer according to the data amplified by the first main amplifier. When the first enable signal is inactive, the first tri-state buffer renders the output node in a high impedance state. The first latch circuit latches and outputs data of the output node of the first tri-state buffer to the outside.
In the above semiconductor memory device, data can be rapidly output to the outside without conducting any timing adjustment in the first latch circuit after activation of the first main amplifier.
When the first enable signal is inactive, the first tri-state buffer renders the output node in the high impedance state. This prevents data held in the first latch circuit from being destroyed.
Preferably, the above semiconductor memory device further includes a second latch circuit and a switch. The switch is connected between the output node of the tri-state buffer and the second latch circuit. In a test mode, the switch connects the output node of the tri-state buffer to the second latch circuit. In a normal mode, the switch disconnects the output node of the tri-state buffer from the second latch circuit.
In the above semiconductor memory device, the switch is provided between the output node of the tri-state buffer and the second latch circuit. This reduces the load on the output buffer as compared to the case where a plurality of normal outputs are electrically gathered at the output end by using a switch or the like and examined as a single test output. This enables signal transmission to a system receiving the output data to be conducted in the same manner as that in the normal mode.
Moreover, the switch provided between the output node of the tri-state buffer and the second latch circuit eliminates the need for timing adjustment of the latch circuit used in the test mode. Accordingly, the test data is rapidly output to the outside without timing control after activation of the first main amplifier.
Preferably, the above semiconductor memory device further includes a second main amplifier, a second tri-state buffer, a second latch circuit, and a switch. The second main amplifier is activated in response to an active second enable signal, and amplifies data read from a second memory cell. When the second enable signal is active, the second tri-state buffer drives an output node of the second tri-state buffer according to the data amplified by the second main amplifier. When the second enable signal is inactive, the second tri-state buffer renders the output node in a high impedance state. The second latch circuit latches and outputs data of the output node of the second tri-state buffer to the outside.
The switch is connected between an output node of the first latch circuit and an output node of the second latch circuit, and is turned ON/OFF according to a bit width of read data.
In the above semiconductor memory device, the switch is provided between the output node of the first latch circuit and the output node of the second latch circuit. This eliminates the need for timing adjustment of the first and second latch circuits even when the bit width of read data is varied.
Preferably, in the above semiconductor memory device, either the first or second latch circuit that is not used is not allowed to conduct latch operation.
The above semiconductor memory device prevents data conflict between the first and second latch circuits.
According to a still further aspect of the present invention, a semiconductor memory device includes an output buffer for outputting data read from a memory cell to an output terminal. The output buffer includes first and second buffers. The first buffer drives the output terminal according to the data read from the memory cell. The second buffer has an active state and an inactive state. In the active state, the second buffer drives the output terminal according to the data read from the memory cell.
The above semiconductor memory device is capable of varying the driving capability of the output buffer by activating and inactivating the second buffer. Preferably, the second buffer is activated and inactivated according to a bit width of the data read from the memory cell.
The above semiconductor memory device is capable of varying the driving capability of the output buffer according to the bit width of the data read from the memory cell. This reduces variation in access time depending on the bit width.
Preferably, the second buffer is activated and inactivated according an external signal capable of recognizing the bit width of the data read from the memory cell.
Preferably, the second buffer is activated and inactivated by using a fuse element representing the bit width of the data read from the memory cell.
Preferably, the semiconductor memory device further includes a detector. The detector detects an operating frequency of the semiconductor memory device. The second buffer is activated and inactivated according to the operating frequency detected by the detector.
The above semiconductor memory device is capable of varying the driving capability of the output buffer according to the operating frequency. This optimizes power consumption.
According to a yet further aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a data line pair, a plurality of first to fourth transistors, a column selection circuit and a write circuit. The plurality of memory cells are arranged in rows and columns. The plurality of word lines are arranged in the rows. The plurality of bit line pairs are arranged in the columns. The plurality of first transistors are connected between a node receiving a first voltage and one bit lines of the plurality of bit line pairs, and are turned ON/OFF in response to a voltage on one data line of the data line pair. The plurality of second transistors are connected between the node and the other bit lines of the plurality of bit line pairs, and are turned ON/OFF in response to a voltage on the other data line of the data line pair. The plurality of third transistors are connected between the plurality of first transistors and one bit lines of the plurality of bit line pairs. The plurality of fourth transistors are connected between the plurality of second transistors and the other bit lines of the plurality of bit line pairs. The column selection circuit applies an active signal to a gate of one of the plurality of third transistors which corresponds to a bit line pair corresponding to a memory cell to be written and applies an active signal to a gate of one of the fourth transistors which corresponds to the bit line pair. When data is written to any of the plurality of memory cells, the write circuit activates one or the other data line of the data line pair according to write data and a level of the first voltage received by the node.
In the above semiconductor memory device, when the node receives a power supply voltage, data can be written to a memory cell by pulling up one or the other bit line of a bit line pair. On the other hand, when the node receives a ground voltage, data can be written to a memory cell by pulling down one or the other bit line of a bit line pair. Accordingly, when the precharge level of the bit line pair becomes higher than a predetermined level, the ground voltage is applied to the node. On the other hand, when the precharge level of the bit line pair becomes lower than the predetermined level, the power supply voltage is applied to the node. This enables write operation to be conducted with a greater margin.
Preferably, the above semiconductor memory device further includes a means for supplying a power supply voltage or a ground voltage to the node as the first voltage according to an address specifying the plurality of memory cells.
The above semiconductor memory device is capable of controlling the voltage level on the node according to the address.
Preferably, the above semiconductor memory device further includes a means for supplying a power supply voltage or a ground voltage to the node as the first voltage according to an operating frequency of the semiconductor memory device.
The above semiconductor memory device is capable of controlling the voltage level on the node according to the operating frequency. This ensures a sufficient write operation margin even when the precharge level of the bit line pairs varies according to the operating frequency.
Preferably, the above semiconductor memory device further includes a means for supplying a power supply voltage or a ground voltage to the node as the first voltage according to a precharge potential of one of the plurality of bit line pairs. The above semiconductor memory device is capable of controlling the voltage level on the node according to the precharge potential of one of the plurality of bit line pairs. This assures a sufficient write operation margin even if the precharge level of the bit line pair varies for other reason.
Preferably, the above semiconductor memory device further includes a means for supplying a power supply voltage or a ground voltage to the node as the first voltage according to external control.
The above semiconductor memory device allows the voltage level on the node to be controlled from the outside. Accordingly, which of the write operation by pulling up one or the other bit line of a bit line pair and the write operation by pulling down one or the other bit line of a bit line pair ensures a greater write operation margin can be examined upon inspecting and evaluating the chips. A write method ensuring a greater write operation margin can be applied based on the examination result.